Atmel AT85DVK-07 Dokumentacja Pobierz pdf (Strona 124)

124

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

1 STALLI

Stall Interrupt Flag

Set by hardware to signal that a STALL handshake has been sent, or that a CRC

error has been detected in a OUT isochronous endpoint.

Shall be cleared by software. Setting by software has no effect.

0 TXINI

Transmitter Ready Interrupt Flag

Set by hardware to signal that the current bank is free and can be filled. An

interrupt (EPINTx) is triggered (if enabled).

Shall be cleared by software to handshake the interrupt. Setting by software has

no effect.

This bit is inactive (cleared) if the endpoint is an OUT endpoint.

Table 127. UEIENX Register

UEIENX (1.D2h) – USB Endpoint Interrupt Enable Register

7 6 5 4 3 2 1 0

FLERRE NAKINE - NAKOUTE RXSTPE RXOUTE STALLE TXINE

Bit

Number

Bit

Mnemonic

Description

7 FLERRE

Flow Error Interrupt Enable Flag

Set to enable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are

sent.

Clear to disable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are

sent.

6 NAKINE

NAK IN Interrupt Enable Bit

Set to enable an endpoint interrupt (EPINTx) when NAKINI is set.

Clear to disable an endpoint interrupt (EPINTx) when NAKINI is set.

5 -

Reserved

The value read from these bits is always 0. Do not set these bits.

4 NAKOUTE

NAK OUT Interrupt Enable Bit

Set to enable an endpoint interrupt (EPINTx) when NAKOUTI is set.

Clear to disable an endpoint interrupt (EPINTx) when NAKOUTI is set.

3 RXSTPE

Received SETUP Interrupt Enable Flag

Set to enable an endpoint interrupt (EPINTx) when RXSTPI is sent.

Clear to disable an endpoint interrupt (EPINTx) when RXSTPI is sent.

2 RXOUTE

Received OUT Data Interrupt Enable Flag

Set to enable an endpoint interrupt (EPINTx) when RXOUTI is sent.

Clear to disable an endpoint interrupt (EPINTx) when RXOUTI is sent.

1 STALLE

Stall Interrupt Enable Flag

Set to enable an endpoint interrupt (EPINTx) when STALLI is sent.

Clear to disable an endpoint interrupt (EPINTx) when STALLI is sent.

0 TXINE

Transmitter Ready Interrupt Enable Flag

Set to enable an endpoint interrupt (EPINTx) when TXINI is sent.

Clear to disable an endpoint interrupt (EPINTx) when TXINI is sent.

Bit

Number

Bit

Mnemonic Description

1 2 ... 119 120 121 122 123 124 125 126 127 128 129 ... 262 263

Atmel AT85DVK-07 Dokumentacja Strona 124

Komentarze do niniejszej Instrukcji

Atmel AT85DVK-07 Dokumentacja Strona 124

Komentarze do niniejszej Instrukcji

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